Energy and Area efficient Carry Select Adder on a reconfigurable hardware

Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations. From the structure of the CSLA, it is clear that there is scope for reducing the gate count and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the logic resources and power of the CSLA. Based on this modification square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced resource utilization and power as compared with the regular SQRT CSLA. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through programmable logic design technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. Keywords— Field programmable Gate Array (FPGA), CSLA, reconfigurable hardware, area-efficient, energy